SRAMS, especially high-density SRAMs utilizing small device geometries, generally incorporate sense amplifiers to provide the output drive capability for memory reads. Each sense amplifier detects the differential voltage across a corresponding pair of complementary bit lines (BL and BL′) in an SRAM array. Outputting correctly sensed bit data from the memory array depends on sense amplifier settling times, which in turn depend on a number of process-related and environmental variables.
For example, the effective capacitance of each SRAM cell, and the number of SRAM cells (rows) connected to the bit lines, influences the charge and discharge times of the bit lines and therefore influences the settling time for reliably sensing differential bit line voltages via the sense amplifiers. Cell capacitance varies with variations in the process—e.g., variations in metallization layer widths—and, more generally, the overall circuit timing changes with process, temperature, and voltage variations.
Designers address read timing variations in a number of ways. One conventional approach generates read clock timing via circuitry that tracks changes in the actual SRAM array. For example, a designer may implement a “dummy” bit line that is loaded with additional SRAM cells that are not part of the actual memory array. By using the same SRAM cells and design rules as the actual bit lines, the charge/discharge times of the dummy bit line proportionally track those of the real bit lines. As such, using the dummy bit line in read clock generation automatically compensates for timing changes in the SRAM array.
However, the use of dummy bit lines is not without certain disadvantages. For example, common existing and developing process technologies do not permit the direct connection of system voltages to transistor gate inputs. Several considerations factor into this design constraint, including electrostatic damage (ESD) concerns.
The constraint is problematic because configuring a dummy bit line requires tying a certain number of the SRAM cells high and the remaining ones low. With direct connections to VDD (power) and VSS (ground or reference) disallowed by the design rules, an additional “tie” structure must be used for each of the standard SRAM cells on the dummy bit line. Each tie structure generally includes two transistors to make the VSS or VDD connection via drain/source paths and the corresponding consumption of real estate by the tie structures can be significant.